Digital integrated circuits are conventionally tested by successively applying test vectors to the inputs of the circuit. Upon receipt of each test vector, which takes the form of a pattern of ones and/or zeros, the circuit responds by producing a response at its outputs, each response also being comprised of a pattern of ones and/or zeros. When the circuit is operating properly, the response at each output of the circuit will match an expected response for each input test vector. If a fault exists, then a mismatch occurs. The higher the percentage of possible faults that can be detected, the greater the confidence of the lack of any faults in the circuit. Achieving 100% fault coverage is very difficult without exhaustive testing. In the past, testing of a circuit has been accomplished by first mathematically modeling the circuit and all its possible faults. Using the mathematical model, a set of test vectors is then generated, which, when successively applied to the circuit, may reveal most of the possible faults. While algorithms for fault simulation and test vector generation exist, applying such algorithms to a circuit of even moderate complexity is a time-consuming task, often requiring weeks or months of effort. As a practical matter, obtaining 100% fault coverage, while desirable, has previously proven impractical.
Thus, there is a need for a technique for achieving 100% fault coverage of a sequential digital integrated circuit without the need for fault simulation or deterministic test generation.